//
// Created by Administrator on 2020/11/11.
//

#ifndef O5G_SRC_O5GUE_LCORE_INCLUDE_L1APIMSG_H_
#define O5G_SRC_O5GUE_LCORE_INCLUDE_L1APIMSG_H_

#include "commMsg.h"

enum
{
    UE_L1_API_MSG_CONFIG_REQ = UE_L1_API_MSG_BASE,
    UE_L1_API_MSG_CONFIG_RSP,
    UE_L1_API_MSG_SYNC_REQ,
    UE_L1_API_MSG_SYNC_RSP,
    UE_L1_API_MSG_STOP_REQ,
    UE_L1_API_MSG_STOP_RSP,
    UE_L1_API_MSG_ERROR_IND,
    UE_L1_API_MSG_SLOT_IND,
    UE_L1_API_MSG_DL_TTI_REQ,
    UE_L1_API_MSG_UL_TTI_REQ,
    UE_L1_API_MSG_DCI_IND,
    UE_L1_API_MSG_TX_DATA_REQ,
    UE_L1_API_MSG_RX_DATA_IND,
    UE_L1_API_MSG_CRC_IND,
    UE_L1_API_MSG_SRS_IND,
    UE_L1_API_MSG_SSB_IND,
    UE_L1_API_MSG_UCI_IND,
    UE_L1_API_MSG_BUTT
};

#define UE_L1_API_MAX_PDUS_PER_SLOT        64
#define UE_L1_API_DCI_PAYLOAD_BYTE_LEN     32

typedef struct UeL1ApiMsgConfigReq
{
    S_UeCommMsgHdr commMsgHdr;
    uint32_t ueIdx;
} S_UeL1ApiMsgConfigReq;

typedef struct UeL1ApiMsgConfigRsp
{
    S_UeCommMsgHdr commMsgHdr;
    uint32_t ueIdx;
} S_UeL1ApiMsgConfigRsp;

typedef struct UeL1ApiMsgSyncReq
{
    S_UeCommMsgHdr commMsgHdr;
    uint32_t ueIdx;
} S_UeL1ApiMsgSyncReq;

typedef struct UeL1ApiMsgSyncRsp
{
    S_UeCommMsgHdr commMsgHdr;
    uint32_t ueIdx;
} S_UeL1ApiMsgSyncRsp;

typedef struct UeL1ApiMsgStopReq
{
    S_UeCommMsgHdr commMsgHdr;
    uint32_t ueIdx;
} S_UeL1ApiMsgStopReq;

typedef struct UeL1ApiMsgStopRsp
{
    S_UeCommMsgHdr commMsgHdr;
    uint32_t ueIdx;
} S_UeL1ApiMsgStopRsp;

typedef struct UeL1ApiMsgErrorInd
{
    S_UeCommMsgHdr commMsgHdr;
    uint32_t ueIdx;
} S_UeL1ApiMsgErrorInd;

typedef struct UeL1ApiMsgSlotInd
{
    S_UeCommMsgHdr commMsgHdr;
    uint32_t ueIdx;
    uint16_t sfn;
    uint16_t slot;
} S_UeL1ApiMsgSlotInd;

typedef struct
{
    uint16_t rnti;
    uint16_t scramblingId;
    uint16_t scramblingRnti;
    uint8_t cceIndex;
    uint8_t aggregationLevel;
//    fapi_precoding_bmform_t pc_and_bform;
    uint8_t beta_pdcch_1_0;
    uint8_t powerControlOffsetSS;
    uint16_t payloadSizeBits;
    uint8_t payload[UE_L1_API_DCI_PAYLOAD_BYTE_LEN]; // 5G FAPI Table 3-37
} S_UeL1ApiDci;

typedef struct
{
    uint16_t bwpSize;
    uint16_t bwpStart;
    uint8_t subCarrierSpacing;
    uint8_t cyclicPrefix;
    uint8_t startSymbolIndex;
    uint8_t durationSymbols;
    uint8_t freqDomainResource[6];
    uint8_t cceRegMappingType;
    uint8_t regBundleSize;
    uint8_t interleaverSize;
    uint8_t coreSetType;
    uint16_t shiftIndex;
    uint8_t precoderGranularity;
    S_UeL1ApiDci dlDci;
} S_UeL1ApiDlPdcchPdu;

typedef struct
{
    uint16_t pduBitMap;
    uint16_t rnti;
    uint16_t pdu_index;
    uint16_t bwpSize;
    uint16_t bwpStart;
    uint8_t subCarrierSpacing;
    uint8_t cyclicPrefix;
    uint8_t nrOfCodeWords;
    uint8_t pad[3];
//    fapi_codeword_pdu_t cwInfo[FAPI_MAX_NUMBER_OF_CODEWORDS_PER_PDU];
    uint16_t dataScramblingId;
    uint8_t nrOfLayers;
    uint8_t transmissionScheme;
    uint8_t refPoint;
    uint8_t dmrsConfigType;
    uint16_t dlDmrsSymbPos;
    uint8_t scid;
    uint8_t numDmrsCdmGrpsNoData;
    uint8_t resourceAlloc;
    uint8_t pad1;
    uint16_t dlDmrsScramblingId;
    uint16_t dmrsPorts;
    uint16_t rbStart;
    uint16_t rbSize;
    uint8_t rbBitmap[36];
    uint8_t vrbToPrbMapping;
    uint8_t startSymbIndex;
    uint8_t nrOfSymbols;
    uint8_t ptrsPortIndex;
    uint8_t ptrsTimeDensity;
    uint8_t ptrsFreqDensity;
    uint8_t ptrsReOffset;
    uint8_t nEpreRatioOfPdschToPtrs;
//    fapi_precoding_bmform_t preCodingAndBeamforming;
    uint8_t powerControlOffset;
    uint8_t powerControlOffsetSS;
    uint8_t isLastCbPresent;
    uint8_t isInlineTbCrc;
    uint32_t dlTbCrc;       // 5G FAPI Table 3-38
    uint8_t mappingType;
    uint8_t nrOfDmrsSymbols;
    uint8_t dmrsAddPos;
    uint8_t pad2;
} S_UeL1ApiDlPdschPdu;

typedef struct
{
    uint16_t bwpSize;
    uint16_t bwpStart;
    uint8_t subCarrierSpacing;
    uint8_t cyclicPrefix;
    uint16_t startRb;
    uint16_t nrOfRbs;
    uint8_t csiType;
    uint8_t row;
    uint16_t freqDomain;
    uint8_t symbL0;
    uint8_t symbL1;
    uint8_t cdmType;
    uint8_t freqDensity;
    uint16_t scramId;
    uint8_t powerControlOffset;
    uint8_t powerControlOffsetSs;
    uint8_t pad[2];
//    fapi_precoding_bmform_t preCodingAndBeamforming;    // 5G FAPI Table 3-39
} S_UeL1ApiDlCsiRsPdu;

//typedef struct
//{
//    uint16_t physCellId;
//    uint8_t betaPss;
//    uint8_t ssbBlockIndex;
//    uint8_t ssbSubCarrierOffset;
//    uint8_t bchPayloadFlag;
//    uint16_t ssbOffsetPointA;
//    uint32_t bchPayload;
////    fapi_precoding_bmform_t preCodingAndBeamforming;    // 5G FAPI Table 3-40
//} S_UeL1ApiDlSsbPdu;

typedef enum
{
    UE_L1_API_DL_TTI_PDU_TYPE_PDCCH  = 0,
    UE_L1_API_DL_TTI_PDU_TYPE_PDSCH  = 1,
    UE_L1_API_DL_TTI_PDU_TYPE_CSI_RS = 2,
    UE_L1_API_DL_TTI_PDU_TYPE_SSB    = 3,
} E_UeL1ApiDlTtiPduType;

typedef struct
{
    uint16_t pduType; // E_UeL1ApiDlTtiPduType
    uint16_t pduSize;
    union
    {
        S_UeL1ApiDlPdcchPdu pdcchPdu;
        S_UeL1ApiDlPdschPdu pdschPdu;
        S_UeL1ApiDlCsiRsPdu csiRsPdu;
//        S_UeL1ApiDlSsbPdu ssbPdu;  // 5G FAPI Table 3-35 Subset
    } pdu;
} S_UeL1ApiDlTtiReqPdu;

typedef struct UeL1ApiMsgDlTtiReq
{
    S_UeCommMsgHdr commMsgHdr;
    uint32_t ueIdx;

    uint16_t sfn;
    uint16_t slot;
    uint8_t pduNum;
    S_UeL1ApiDlTtiReqPdu pdus[UE_L1_API_MAX_PDUS_PER_SLOT]; // 5G FAPI Table 3-35
} S_UeL1ApiMsgDlTtiReq;

typedef struct {
    uint16_t physCellId;
    uint8_t numPrachOcas;
    uint8_t prachFormat;
    uint8_t numRa;
    uint8_t prachStartSymbol;
    uint16_t numCs;
//    fapi_ul_rx_bmform_pdu_t beamforming;
} S_UeL1ApiUlPrachPdu;      // 5G FAPI Table 3-45

typedef struct {
    uint16_t pduBitMap;
    uint16_t rnti;
    uint32_t handle;
    uint16_t bwpSize;
    uint16_t bwpStart;
    uint8_t subCarrierSpacing;
    uint8_t cyclicPrefix;
    uint8_t mcsIndex;
    uint8_t mcsTable;
    uint16_t targetCodeRate;
    uint8_t qamModOrder;
    uint8_t transformPrecoding;
    uint16_t dataScramblingId;
    uint8_t nrOfLayers;
    uint8_t dmrsConfigType;
    uint16_t ulDmrsSymbPos;
    uint16_t ulDmrsScramblingId;
    uint8_t scid;
    uint8_t numDmrsCdmGrpsNoData;
    uint16_t dmrsPorts;
    uint16_t nTpPuschId;
    uint16_t tpPi2Bpsk;
    uint8_t rbBitmap[36];
    uint16_t rbStart;
    uint16_t rbSize;
    uint8_t vrbToPrbMapping;
    uint8_t frequencyHopping;
    uint16_t txDirectCurrentLocation;
    uint8_t resourceAlloc;
    uint8_t uplinkFrequencyShift7p5khz;
    uint8_t startSymbIndex;
    uint8_t nrOfSymbols;
    uint8_t mappingType;
    uint8_t nrOfDmrsSymbols;
    uint8_t dmrsAddPos;
    uint8_t pad;

//    fapi_pusch_data_t puschData;
//    fapi_pusch_uci_t puschUci;
//    fapi_pusch_ptrs_t puschPtrs;
//    fapi_dfts_ofdm_t dftsOfdm;
//    fapi_ul_rx_bmform_pdu_t beamforming;    // 5G FAPI Table 3-46
} S_UeL1ApiUlPuschPdu;

typedef struct {
    uint16_t rnti;
    uint8_t pad1[2];
    uint32_t handle;
    uint16_t bwpSize;
    uint16_t bwpStart;
    uint8_t subCarrierSpacing;
    uint8_t cyclicPrefix;
    uint8_t formatType;
    uint8_t multiSlotTxIndicator;
    uint8_t pi2Bpsk;
    uint8_t pad2;
    uint16_t prbStart;
    uint16_t prbSize;
    uint8_t startSymbolIndex;
    uint8_t nrOfSymbols;
    uint8_t freqHopFlag;
    uint8_t groupHopFlag;
    uint8_t sequenceHopFlag;
    uint8_t pad3;
    uint16_t secondHopPrb;
    uint16_t hoppingId;
    uint16_t initialCyclicShift;
    uint16_t dataScramblingId;
    uint8_t timeDomainOccIdx;
    uint8_t preDftOccIdx;
    uint8_t preDftOccLen;
    uint8_t addDmrsFlag;
    uint16_t dmrsScramblingId;
    uint8_t dmrsCyclicShift;
    uint8_t srFlag;
    uint16_t bitLenHarq;
    uint8_t pad4[2];
    uint16_t bitLenCsiPart1;
    uint16_t bitLenCsiPart2;
//    fapi_ul_rx_bmform_pdu_t beamforming;    // 5G FAPI Table 3-51
} S_UeL1ApiUlPucchPdu;

typedef struct {
    uint16_t rnti;
    uint8_t pad[2];
    uint32_t handle;
    uint16_t bwpSize;
    uint16_t bwpStart;
    uint8_t subCarrierSpacing;
    uint8_t cyclicPrefix;
    uint8_t numAntPorts;
    uint8_t numSymbols;
    uint8_t numRepetitions;
    uint8_t timeStartPosition;
    uint8_t configIndex;
    uint8_t bandwidthIndex;
    uint16_t sequenceId;
    uint8_t combSize;
    uint8_t combOffset;
    uint8_t cyclicShift;
    uint8_t frequencyPosition;
    uint16_t frequencyShift;
    uint8_t frequencyHopping;
    uint8_t groupOrSequenceHopping;
    uint8_t resourceType;
    uint8_t pad1[2];
    uint16_t tSrs;
    uint16_t tOffset;
//    fapi_ul_rx_bmform_pdu_t beamforming;    // 5G FAPI Table 3-52
} S_UeL1ApiUlSrsPdu;

typedef enum
{
    UE_L1_API_UL_TTI_PDU_TYPE_PRACH  = 0,
    UE_L1_API_UL_TTI_PDU_TYPE_PUSCH  = 1,
    UE_L1_API_UL_TTI_PDU_TYPE_PUCCH  = 2,
    UE_L1_API_UL_TTI_PDU_TYPE_SRS    = 3,
} E_UeL1ApiUlTtiPduType;

typedef struct {
    uint16_t pduType; // E_UeL1ApiUlTtiPduType
    uint16_t pduSize;
    union {
        S_UeL1ApiUlPrachPdu prach_pdu;
        S_UeL1ApiUlPuschPdu pusch_pdu;
        S_UeL1ApiUlPucchPdu pucch_pdu;
        S_UeL1ApiUlSrsPdu srs_pdu;
    } pdu;
} S_UeL1ApiUlTtiReqPdu;    // 5G FAPI Subset Table 3-44

typedef struct UeL1ApiMsgUlTtiReq
{
    S_UeCommMsgHdr commMsgHdr;
    uint32_t ueIdx;

    uint16_t sfn;
    uint16_t slot;
    uint8_t pduNum;
    S_UeL1ApiUlTtiReqPdu pdus[UE_L1_API_MAX_PDUS_PER_SLOT]; // 5G FAPI Table 3-35
} S_UeL1ApiMsgUlTtiReq;

typedef struct UeL1ApiMsgDciInd
{
    S_UeCommMsgHdr commMsgHdr;
    uint32_t ueIdx;
} S_UeL1ApiMsgDciInd;

typedef struct {
    uint16_t pduType; // E_UeL1ApiRxDataPduType
    uint16_t pduSize;
    uint8_t  pdu[8192];
} S_UeL1ApiMsgTxDataPdu;

typedef struct UeL1ApiMsgTxDataReq
{
    S_UeCommMsgHdr commMsgHdr;
    uint32_t ueIdx;
    uint8_t pduNum;
    S_UeL1ApiMsgTxDataPdu pdus[UE_L1_API_MAX_PDUS_PER_SLOT];
} S_UeL1ApiMsgTxDataReq;

typedef enum
{
    UE_L1_API_RX_DATA_PDU_TYPE_SSB   = 0,
    UE_L1_API_RX_DATA_PDU_TYPE_RAR   = 1,
    UE_L1_API_RX_DATA_PDU_TYPE_DLSCH = 2,
} E_UeL1ApiRxDataPduType;

typedef struct {
    uint16_t pduType; // E_UeL1ApiRxDataPduType
    uint16_t pduSize;
    uint8_t  pdu[8192];
} S_UeL1ApiMsgRxDataPdu;

typedef struct UeL1ApiMsgRxDataInd
{
    S_UeCommMsgHdr commMsgHdr;
    uint32_t ueIdx;
    uint8_t pduNum;
    S_UeL1ApiMsgRxDataPdu pdus[UE_L1_API_MAX_PDUS_PER_SLOT];
} S_UeL1ApiMsgRxDataInd;

typedef struct UeL1ApiMsgCrcInd
{
    S_UeCommMsgHdr commMsgHdr;
    uint32_t ueIdx;
} S_UeL1ApiMsgCrcInd;

typedef struct UeL1ApiMsgSrsInd
{
    S_UeCommMsgHdr commMsgHdr;
    uint32_t ueIdx;
} S_UeL1ApiMsgSrsInd;

typedef struct UeL1ApiMsgSsbInd
{
    S_UeCommMsgHdr commMsgHdr;
    uint32_t ueIdx;
    uint16_t physCellId;
    uint8_t betaPss;
    uint8_t ssbBlockIndex;
    uint8_t ssbSubCarrierOffset;
    uint8_t bchPayloadFlag;
    uint16_t ssbOffsetPointA;
    uint32_t bchPayload;
//    fapi_precoding_bmform_t preCodingAndBeamforming;    // 5G FAPI Table 3-40
} S_UeL1ApiMsgSsbInd;

typedef struct UeL1ApiMsgUciInd
{
    S_UeCommMsgHdr commMsgHdr;
    uint32_t ueIdx;
} S_UeL1ApiMsgUciInd;

#endif //O5G_SRC_O5GUE_LCORE_INCLUDE_L1APIMSG_H_
